Differential amplifier

ABSTRACT

A differential amplifier has a pair of inputs and a pair of outputs. Each of the outputs is connected between a high potential source and a low potential source through a pair of FETs, respectively. These FETs have the same conduction type. A gate of one of the FETs is connected to one of the inputs, and a gate of the other FET is connected to the other input. This arrangement suppresses output offset and realizes a wide sensitivity range.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a differential amplifier made of asemiconductor material and particularly to a differential amplifierhaving a wide sensitivity range.

2. Description of the Prior Art

FIG. 1 is a circuit diagram showing a differential amplifier accordingto a first embodiment of the prior art. FIG. 2 is a circuit diagramshowing a simplified circuit of the differential amplifier of FIG. 1.FIG. 3 shows voltage-current characteristic curves of the circuit ofFIG. 2.

FIG. 4 is a circuit diagram showing a differential amplifier accordingto a second embodiment of the prior art. FIG. 5 a circuit diagramshowing a simplified circuit of the differential amplifier of FIG. 4.FIG. 6 shows voltage-current characteristic curves of the circuit FIG.5.

The differential amplifier of the first prior art embodiment of FIGS. 1to 3 will be explained.

In FIG. 1, MOSFETs Q1 and Q4 form a pair of inverters, and MOSFETs Q2and Q5 another pair of inverters. A MOSFET Q3 is a constant currentMOSFET. For the sake of simplicity of explanation, the MOSFET Q3 of FIG.1 is removed in FIG. 2 with reference to which a differential gain andan offset of the differential amplifier of the first prior artembodiment will be explained.

When a voltage V0 is applied to input terminals IN1 and IN2 in FIG. 2,an operating point of the differential amplifier will be a point M inFIG. 3.

When ±ΔV is applied to the input terminals INl and IN2, output terminalsOUT1 and OUT2 provide a potential difference represented with points Land H in FIG. 3. This potential difference is called the differentialgain.

When a voltage of V0+ΔV is applied to the input terminals IN1 and IN2, avoltage at each of the output terminals OUT1 and OUT2 shifts from theoperating point M to an operating point M'. When a voltage of V0-ΔV isapplied to the input terminals IN1 and IN2, a voltage at each of theoutput terminals OUT1 and OUT2 shifts from the operating point M to anoperating point M". This is called the offset, which indicates a shiftof the operating point.

In this way, according to the differential amplifier of the first priorart embodiment, an increase in the differential offset inevitablyaccompanies an increase in the gain, so that this differential amplifierachieves a narrow sensitivity range.

The differential amplifier of the second prior art embodiment will beexplained with reference to FIGS. 4 to 6.

In FIG. 4, MOSFETs Q1 and Q4 form a pair of inverters, and MOSFETs Q2and Q5 form another pair of inverters. Each pair of the inverters has aCMOS configuration. For the sake of simplicity of explanation, a MOSFETQ3 of FIG. 4 is removed in FIG. 5 with reference to which a principle ofthe second prior art embodiment will be explained.

When a voltage V0 is applied to input terminals IN1 and IN2 in FIG. 5,an operating point of the differential amplifier will be a point M inFIG. 6.

When ±ΔV is applied to the input terminals IN1 and IN2, output terminalsOUT1 and OUT2 provide a potential difference represented with points Land H in FIG. 3. This potential difference is the differential output.

When the input voltage is changed from V0 to V0+ΔV, the operating pointis shifted to a point M', and when the input voltage is changed toV0-ΔV, the operating point is shifted to a point M".

Since the differential amplifier of the second prior art embodiment hasthe inverter pairs of CMOS configuration, it may provide a largedifferential gain but with a large offset. Namely, this differentialamplifier achieves a very narrow sensitivity range.

In this way, the conventional differential amplifiers may provide alarge differential gain but with a large offset which drasticallynarrows a sensitivity range of the amplifiers.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a differentialamplifier having a wide sensitivity range.

Another object of the present invention is to provide a differentialamplifier having a large differential gain and a small offset.

In order to accomplish the objects, the present invention provides adifferential amplifier comprising first and second different potentialsources, a first output terminal connected to the first potential sourcethrough a first FET and to the second potential source through a secondFET, the first and second FETs having the same conduction type, a secondoutput terminal connected to the first potential source through a thirdFET and to the second potential source through a fourth FET, the thirdand fourth FETs having the same conduction types, a first input terminalconnected to gates of the first and fourth FETs, and a second inputterminal connected to gates of the second and third FETs.

In this arrangement, all of the FETs may have the same conduction type,so that the arrangement may be formed in a small area on a semiconductorchip.

These and other objects, features and advantages of the presentinvention will be more apparent from the following detailed descriptionof preferred embodiments in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a differential amplifier accordingto a first prior art embodiment;

FIG. 2 is a circuit diagram showing a simplified circuit of thedifferential amplifier of FIG. 1;

FIG. 3 is a graph showing voltage-current characteristic curves of thecircuit of FIG. 2;

FIG. 4 is a circuit diagram showing a differential amplifier accordingto a second prior art embodiment;

FIG. 5 is a circuit diagram showing a simplified circuit of thedifferential amplifier of FIG. 4;

FIG. 6 is a graph showing voltage-current characteristic curves of thecircuit of FIG. 5;

FIG. 7 is a circuit diagram showing a differential amplifier accordingto a first embodiment of the invention;

FIG. 8 is a circuit diagram showing a simplified circuit of thedifferential amplifier of FIG. 7;

FIG. 9 is a graph showing voltage-current characteristic curves of thecircuit of FIG. 8;

FIG. 10 is a circuit diagram showing a differential amplifier accordingto a second embodiment of the invention;

FIG. 11 is a circuit diagram showing a differential amplifier accordingto a third embodiment of the invention;

FIG. 12 is a circuit diagram showing a differential amplifier accordingto a fourth embodiment of the invention;

FIG. 13 is a circuit diagram showing a differential amplifier accordingto a fifth embodiment of the invention;

FIG. 14 is a circuit diagram showing a differential amplifier accordingto a sixth embodiment of the invention;

FIG. 15 is a circuit diagram showing a differential amplifier accordingto a seventh embodiment of the invention; and

FIG. 16 is a circuit diagram showing a differential amplifier accordingto an eighth embodiment of the invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 7 shows a differential amplifier according to the first basicembodiment of the invention.

This differential amplifier comprises a first MOSFET Q1 having a drainconnected to a first output terminal OUT1, a gate connected to a firstinput terminal IN1 and a source connected to a first node T1; a secondMOSFET Q2 having a drain connected to a second output terminal OUT2, agate connected to a second input terminal IN2 and a source connected tothe first node T1; a current controlling third MOSFET Q3 having a drainconnected to the first node T1 and a source connected to a first powersource P1; a fourth load MOSFET Q4 having a drain connected to a secondpower source P2, a gate connected to the second input terminal IN2 and asource connected to the first output terminal OUT1; and a fifth loadMOSFET Q5 having a drain connected to the second power source P2, a gateconnected to the first input terminal IN1 and a source connected to thesecond output terminal OUT2.

The first through fifth MOSFETs Q5 have the same conduction type, thefirst and second MOSFETs Q1 and Q2 have the same dimensions, and thefourth and fifth MOSFETs have the same dimensions. All of the FETs areenhancement FETs.

An operation of the differential amplifier of FIG. 7 will be explainedwith reference to FIGS. 8 and 9, in which FIG. 8 has no constant currentMOSFET Q3 of FIG. 7 for the sake of simplicity of explanation, and FIG.9 shows voltage-current characteristic curves of the circuit of FIG. 8.

When a voltage V0 is applied to the input terminals IN1 and IN2, theoperating point of the differential amplifier will be point M in FIG. 9.

When a voltage difference of ±ΔV is applied to the input terminals IN1and IN2, current characteristics of the driver MOSFET Q1 and of the loadMOSFET Q4 change, so that the output terminals OUT1 and OUT2 provide apotential difference represented with points L and H in FIG. 9. Thispotential difference is a differential gain.

When the voltage applied to the input terminals IN1 and IN2 changes fromV0 to V0+ΔV, the operating point shifts from M to M', and when theapplied voltage changes to V0-ΔV, the operating point shifts to M". Thisis an offset. As is apparent from FIG. 9, this offset is suppressed to avery small value.

In this way, the differential amplifier of this embodiment has a largedifferential gain and a very small offset. Since the MOSFETs Q1 throughQ5 have the same conduction type, they may be formed in a small area inthe same well.

FIG. 10 shows a differential amplifier according to the secondembodiment of the invention, with load MOSFETs Q4 and Q5 being n-channeldepletion MOSFETs. Compared with enhancement MOSFETs, the depletionMOSFETs Q4 and Q5 increase an upper limit of an output voltage.

The embodiments only show basic arrangements. It is possible to arrangeload MOSFETs between the second power source P2 and the MOSFETs Q4 andQ5, between the MOSFETs Q4 and Q1, between the MOSFETs Q5 and Q2, orbetween the MOSFET Q3 and the first power source P1 in series.

FIG. 11 shows a differential amplifier according to the third embodimentof the invention, in which an output terminal OUT1 is fed back to aMOSFET Q3, thereby further reducing the offset.

FIG. 12 shows a differential amplifier according to the fourthembodiment of the invention, in which properly biased resistance loadPMOSFETs Q6 and Q7 are connected to MOSFETs Q4 and Q5 in parallel,respectively, to increase an upper limit voltage of output terminalsOUT1 and OUT2 to the voltage of a second power source P2.

FIG. 13 shows a differential amplifier according to the fifth embodimentof the invention, in which PMOSFETs Q6 and Q7 forming CMOSconfigurations with MOSFETs Q1 and Q2 are connected to MOSFETs Q4 and Q5in parallel, respectively, to further increase the differential gain.

FIG. 14 shows a differential amplifier according to the sixth embodimentof the invention, in which properly biased resistance load NMOSFETs Q6and Q7 are connected to MOSFETs Q4 and Q5 in parallel, respectively.

FIG. 15 shows a differential amplifier according to the seventhembodiment of the invention, in which PMOSFETs Q6 and Q7 are positivelyfed back from opposite output terminals OUT2 and OUT1, respectively, andconnected to MOSFETs Q4 and Q5 in parallel, respectively.

In the embodiments shown in FIGS. 10 to 15, the driver MOSFETs Q1 and Q2are NMOSFETs. According to the invention, it is possible to analogicallyinvert the PMOSFETs and NMOSFETs of each of the embodiments. An exampleof this is shown in FIG. 16, in which, contrary to FIG. 10, a commonpower source P1 is connected to a constant current MOSFET Q3.

In summary, the present invention provides a differential amplifierachieving a large differential gain and a small offset, i.e., a widesensitivity range. Since driver MOSFETs and load MOSFETs of thedifferential amplifier of the invention have the same conduction type,these MOSFETs may be formed in a small area in the same well.

Various modifications will become possible for those skilled in the artafter receiving the teachings of the present disclosure withoutdeparting from the scope thereof.

What is claimed is:
 1. A differential amplifier comprising:a firstpotential source; a second potential source; a first FET connected tosaid first potential source; a second FET connected to said secondpotential source; a third FET connected to said first potential source;a fourth FET connected to said second potential source; a first outputterminal connected directly to a junction between said first and secondFETs; a second output terminal connected directly to a junction betweensaid third and fourth FETs; a first input terminal connected to gates ofthe first and fourth FETs; and a second input terminal connected togates of the second and third FETs, wherein an ON state at said secondFET is weakened and an ON state at said fourth FET is strengthened whena high potential and a low potential are loaded in said first inputterminal and said second input terminal, respectively, so that a currentflows from said second potential source to said second output terminal,thus increasing an amplifying efficiency of said differential amplifier.2. The differential amplifier according to claim 1, wherein the firstand third FETs are connected to said first potential source through aconstant current source.
 3. The differential amplifier according toclaim 2, wherein the constant current source is a fifth FET.
 4. Thedifferential amplifier according to claim 1, wherein the first, second,third and fourth FETs have the same conduction type.
 5. The differentialamplifier according to claim 4, wherein the first, second, third andfourth FETs are of n type, and said second potential source provides ahigher potential than said first potential source.
 6. The differentialamplifier according to claim 3, wherein the second and fourth FETs aredepletion FETs, and the first and third FETs are enhancement FETs.
 7. Adifferential amplifier comprising:a first potential source; a secondpotential source providing a higher potential than said first potentialsource; a first N-type FET connected to said first potential sourcethrough a constant current source; a second N-type FET connected to saidsecond potential source; a third N-type FET connected to said firstpotential source through said constant current source; a fourth N-typeFET connected to said second potential source; a fifth FET which servesas said constant current source; a first output terminal connected to agate of said fifth FET; a second output terminal connected directly to ajunction between said third and fourth N-type FETs; a first inputterminal connected to gates of said first and fourth FETs; and a secondinput terminal connected to gates of said second and third FETs, whereinsaid second and fourth FETs are depletion FETs, and said first and thirdFETs are enhancement FETs.
 8. The differential amplifier according toclaim 7, further comprising sixth and seventh FETs connected to thesecond and fourth FETs in parallel, respectively, the conduction type ofthe sixth and seventh FETs being opposite to that of the second andfourth FETs.
 9. The differential amplifier according to claim 8, whereina predetermined bias potential is applied to gates of the sixth andseventh FETs.
 10. The differential amplifier according to claim 8,wherein a gate of the sixth FET is connected to said first inputterminal, and a gate of the seventh FET is connected to said secondinput terminal.
 11. The differential amplifier according to claim 8,wherein a gate of the sixth FET is connected to said second outputterminal, and a gate of the seventh FET is connected to said firstoutput terminal.
 12. The differential amplifier according to claim 7,further comprising eighth and ninth depletion FETs connected to thesecond and fourth FETs in parallel, respectively, the eighth and ninthFETs having the same conduction type as that of the second and fourthFETs.
 13. The differential amplifier according to claim 12, wherein apredetermined bias potential is applied to gates of the eighth and ninthFETs.
 14. The differential amplifier according to claim 12, wherein agate of the eighth FET is connected to said first input terminal, and agate of the ninth FET is connected to said second input terminal.